1. Field of the Invention
The present invention relates to analog to digital conversion.
2. Description of Related Art
In order to test semiconductor (IC) devices of the type used in DVD, set-top boxes and game controllers, HDTV, xDSL and cellular baseband applications, high-performance digital and analog capabilities are required.
In particular, these applications require analog to digital (A/D) converters with a very high sample rate, on the order of 80 Msps(mega samples per second), high resolution such as 14–16 digital output bits and high input bandwidth, above 100 MHz.
In these applications, some popular techniques such as successive approximation analog to digital converters, sigma-delta and flash converters are no longer appropriate.
Sigma-delta technique is used for very high resolution A/D converters such as 20–24 bits, but with very low sampling rate in the order of few ksps. This technique is based on the concept of oversampling with a high factor rate and then decimating to obtain extremely low noise and thus a high number of bits. However, this technique cannot be used in applications requiring sampling rates on the order of several tens of Msps.
Successive approximation A/D converters require a relatively long time for the conversation. Flash A/D converters are relatively fast, but generally low resolution (no more than 10 bits). Therefore both of these techniques are not well suited for the above mentioned applications.
Pipeline converters are better for the aforementioned applications. Today's state-of-the-art pipeline converter technology can provide spurious free dynamic range (SFDR) on the order of 100 dB, very high input bandwidth on the order of a few hundreds of MHz and a sampling frequency of up to 100 Msps.
A problem of pipeline converters, though, is their minimum sampling frequency requirement. A general rule of thumb for these converters is that the minimum sampling frequency is on the order of about one tenth of their maximum sampling frequency. Therefore, for high speed pipeline converters in the range of 80 Msps, a minimum sampling frequency requirement between 1 and 10 Msps should be expected. This may not be a problem in applications where the sampling frequency is not required to vary beyond a relatively limited range, but is a limitation in many automated test equipment (ATE) applications.
Thus, a need has developed for a high speed, high resolution analog to digital conversion system that allows for low speed sampling of data as well.
In order to increase the cost benefit of the investment made in this technology, test engineers want use these pipeline analog to digital converters to test a wider range of semiconductor (IC) devices and in several kinds of applications, such as either linearity testing of D/A converters or testing with an undersampling technique. This latter technique requires analog to digital converters with high bandwidth and high performance, but with relatively low sampling frequency. Linearity testing of D/A converters instead may imply that the A/D converter would receive trains of pulses separated by no operation intervals; overall, the A/D converter would receive a non periodic pattern of samples.
Therefore, for certain applications where a pipeline A/D converter is used in ATE, a system that allows the A/D converter to function when the samples are at a rate below its nominal minimum sampling frequency is needed.